In general, the WLCSP is known as a packaging technique effective for downsizing a semiconductor device. In a semiconductor device to which the WLCSP is applied, packaging is completed in such a wafer state that a plurality of semiconductor chips aggregate, and the size of each semiconductor chip cut by dicing corresponds to a package size.
For example, FIG. 7 of Patent Document 1 discloses for a chip size package including an LSI (semiconductor chip) of a chip size, a passivation film formed on the LSI, epoxy resin formed on the passivation film, bumps formed in the epoxy resin to pass through the same in the thickness direction thereof, and solder balls arranged on forward ends of the bumps. On peripheral edge portions of the LSI, electrodes of the same number as the bumps are provided on the front surfaces thereof. Further, a wiring metal for moving the positions of the solder balls inward beyond the positions of the electrodes along the front surface of the LSI is formed on the passivation film. This wiring metal is connected with the bumps on positions inward beyond the electrodes.